Digital Verification Engineer

2 weeks ago

Pasig, National Capital Region, Philippines Power Integrations Full time $30,000 - $60,000 per year

Description


Description:   Based in our Manila office you will work closely with colleagues locally and in the other IC Design Centres to verify all the digital functions of the mixed signal products developed by Power Integrations. This will include:

  • Creating the digital verification plan based on the design specifications. 
  • Implementing scalable testbenches, including checkers, reference models and coverage groups in SystemVerilog. 
  • Implementing sufficient self-testing, directed and random tests to complete the test plan and coverage goals. 
  • Developing suitable behavioural models to help accelerate mixed-signal simulation. 
  Education & Experience:
  • MSc/MEng or PhD in Electronics Engineering or related subject.
  • Minimum 3 years experience in digital IC verification using industry standard verification methods.
  Requirements:
  • Have good knowledge and understanding of best-practice digital verification methods (e.g. UVM, SVA, coverage, etc.).
  • Be fully conversant with the SystemVerilog standard.
  • Be familiar with writing digital verification plans based on system-level specification documents.
  • Proven experience implementing a full digital verification environment for a mixed-signal IC.
  • Proven experience creating test cases/sequences to achieve the desired level of coverage.
  • Have experience building a regression suite to automatically run all test cases/sequences.
  • Have experience using additional digital verification methods (formal, linting, etc.).
  • Have experience with scripting languages such as TCL/Python.
  • Have experience producing accurate and complete documentation.
  Main Responsibilities:
  • Contribute to the digital verification plan for each product based on the system-level specification.
  • Implement a suitable digital verification environment for each product using industry standard methodologies (e.g. UVM).
  • Create behavioural models (SV-RNM) of internal/external non-digital functions to enable system simulation and verification
  • Create sufficient test cases and sequences to cover all items in the verification plan and meet the coverage requirements.
  • Create and maintain a regression environment for automatically verifying digital/system functions at each stage of the design cycle.
  • Generate all necessary design documentation and participate in design reviews.
  • Contribute to digital verification methodology improvements within the company.

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