Design Verification Engineer

2 days ago

Makati City, National Capital Region, Philippines Sysgen RPO, Inc. Full time $104,000 - $130,878 per year

We are adding a Digital Verification Engineer skilled in Verification and Debug of high-speed I/O Circuits.

Responsibilities may include, but are not limited to:

  • Verification plan for high speed sub-systems including ethernet, DDR.
  • Define coverage goals with corner cases and metrics aligning with standards
  • Understand microarchitecture to ID verification critical paths
  • Perform functional and timing simulations using EDA tools (Synopsis VCS, Cadence Xcellium, Questa)
  • Build and Develop reusable UVM testbenches for block and chip level Verification
  • Validate timing closure and signal integrity across high-speed interfaces
  • Collaborate with designers to simulate digital and AMS blocks
  • Drive code coverage closure
  • Debug failing test cases using waveform viewers, assertion logs, and transaction level traces
  • Establish and maintain regression to ensure continuous verification of evolving RTL
  • Interact with cross functional teams to align DV Goals. Participate in design reviews and ensure system level requirements
  • Support pre-silicon bring up and debug of silicon prototypes.

Qualifications – Minimum Requirements:

  • 7+ years Digital Design Verification experience of complex high speed IO sockets
  • Proficiency in System Verilog and UVM for testbench development and functional verification
  • EDA tool experience (Synopsis VCS, Cadence Xcelium, Siemens Questa and Waveform viewers (Simvision, Verdi)
  • Protocol Verificaiton of High-Speed I/O Circuits (ethernet, DDR)
  • Solid understanding of timing analysis, signal integrity and mixed signal simulations
  • Scripting languages (Python, PERL, TCL)
  • Execute coverage driven verification plans
  • Debuggin Complex RTL issues
  • Formal Verification and assertion based techniques.

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