High Performance Analog Circuit Design Lead

2 days ago

Ayala Alabang, National Capital Region, Philippines beBeeLayout Full time ₱900,000 - ₱1,200,000
Senior Analog Layout Engineer Job Description">

We are seeking a highly skilled Senior Analog Layout Engineer to lead the layout design and optimization of complex analog and mixed-signal integrated circuits. This role involves full ownership of the layout process, including floor planning, verification, and signoff, as well as technical leadership and mentorship for junior engineers.

">

The ideal candidate will have deep expertise in advanced layout techniques and process technologies.

">Responsibilities">
  • ">
  • Owning the physical layout of large and complex analog and mixed-signal blocks, such as data converters, PLLs, power management ICs, and full-chip floor planning.">
  • Applying advanced layout techniques for matching, isolation, shielding, and parasitic minimization to ensure the highest performance.">
  • Taking responsibility for the full DRC and LVS verification flow, working closely with the verification team to resolve any issues and ensure clean signoff.">
  • Providing mentorship and technical guidance to junior and intermediate layout engineers, sharing best practices and reviewing their work.">
  • Collaborating with design engineers, verification engineers, and other stakeholders to ensure design goals are achieved.">
  • Performing post-layout simulations and assisting in debugging layout-related silicon issues during the validation phase.">
  • Continuously seeking ways to improve layout methodologies and workflows for better efficiency and quality.">
">Requirements">
  • ">
  • Bachelor's degree in Electrical Engineering, Microelectronics, or related field. Master's/PhD is a plus.">
  • 5+ years of experience in analog/mixed-signal IC layout, with a proven track record of leading complex layout projects and successful tape outs.">
  • Expert knowledge of analog layout methodologies and tools (e.g., Cadence Virtuoso).">
  • Strong understanding of advanced process technologies (e.g., FinFET, CMOS) and their impact on layout design.">
  • Experience with full-chip layout, including top-level floor planning, integration, and ESD design.">
  • Familiar with DRC, LVS, parasitic extraction, and post-layout simulation flows.">
">What We Offer">
  • ">
  • A dynamic and supportive work environment.">

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