Firmware Engineer Manager, BootROM and Simulation Modeling

Firmware Engineer Manager, BootROM and Simulation Modeling San Jose Astera Labs (NASDAQ: ALAB)provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at Job Overview As the Firmware Engineering Manager , you will lead development and simulation efforts for the BootROM firmware and its supporting SoC models, enabling early architectural validation and robust hardware/firmware co-design. This role requires deep experience in BootROM architecture, security subsystem integration (DICE, attestation, cryptography), and SystemC/TLM simulation modeling to accurately emulate SoC behavior during bring-up and pre-silicon validation. Key Responsibilities Drive the architecture and design strategy for the HW/SW security subsystem, ensuring robust integration of DICE and Attestation functionality in the BootROM. Plan and implement BootROM features: work closely with Security Council and Product Marketing to prioritize the features, create development and validation plan, execute the plan, and communicate status. Develop simulation models: create and validate SystemC/TLM models for SoC components, ensuring accurate representation of hardware behavior for BootROM development and testing. Co-develop hardware/firmware interfaces: work closely with RTL designers to define SoC interfaces to crypto engines and debug/management interfaces, ensuring robust integration. Co-simulate RTL and firmware: conduct co-simulation to identify bugs and propose enhancements, focusing on PCIe Link Training and Status State Machine (LTSSM) and Ethernet link equalization at 100G–800G, collaborating with design/verification teams to implement fixes. Demonstrate entrepreneurial mindset, customer-oriented approach, and professional communication skills for preparing and leading meetings with internal teams and CSPs. Required Experience Bachelor’s or Master’s in Electrical Engineering, Computer Engineering, or Computer Science, with a focus on embedded systems or digital design. 10–15 years developing or supporting firmware for complex SoC/silicon products in compute, networking, or storage applications, with hands‑on experience in microcontroller subsystems (e.g., ARM or equivalent). Expertise in SoC microcontroller architectures, including memory, interrupts, and peripherals. Experience with cosim and simulation environments. Experience with SystemC/TLM modeling. In‑depth understanding of DICE requirements. Preferred Experience Experience leading small teams in an agile, hands‑on manner — planning sprints, assigning tasks based on strengths/aspirations, providing constructive feedback, tracking project status, and addressing execution gaps. Experience with cryptography and the Caliptra subsystem is highly desirable. Experience in FIPS 140 certification and OCP S.A.F.E. audits will set the prospective candidate apart. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non‑binary people, veterans, parents, and individuals with disabilities. #J-18808-Ljbffr