Senior Applications Engineer – DDR Design IP

3 weeks ago

San Jose, Philippines Cadence Design Systems, Inc. Full time

Description The Cadence IP team develops industry leading IPs that enable customers in a variety of markets - from the endpoint to the edge to the cloud. At Cadence we’re helping set the standard on IP products that get integrated in SoCs that power the world’s Data Centers, Automobiles, Cloud and Wireless Systems. We offer amazing opportunities to grow in your career. We are growing our Memory IP presales team and we are looking for smart, energetic, collaborative and creative people to help us lead the industry with our IP products. At Cadence, we believe in embracing diverse ideas and striving for excellence in all that we do. Do you want to make a difference and be challenged? Join the High-Performance Culture at Cadence. As a Technical Presales Engineer, you will support the technical presales of DDR IP by generating collateral through simulations, synthesis and publications. As you grow into more senior roles, you will use your knowledge of different memory interface standards to architect memory solutions for customers using Cadence DDR IP. This role offers the benefit of both technical growth and business skill development. You will be part of the Technical Field Organization helping educate customers and providing solutions using our DDR IP portfolio. Our memory PHY and controller IPs are used in data centers, mobile devices, automobiles and consumer devices. Responsibilities include: Technical presales of Memory IP Gain expertise in memory controller and PHY IPs and DDR protocols Work closely with IP Sales staff, marketing and R&D teams to win opportunities Run Verilog simulations to enable IP benchmarking Run RTL synthesis for area and timing analysis Present IP demos to customers Travel to customer sites may be required occasionally Qualifications: BS / MS in EE, CE or related majors Knowledge of Computer Architecture and Electronics circuits Knowledge of Verilog HDL Experience with simulation and synthesis tools Excellent presentation skills and verbal / written communication skills is a must Nice to have: Familiarity with one or more DRAM protocols – DDR4 / 5, LPDDR4 / 5 / 5X, HBM2 / 3, GDDR6 Perl / Python Scripts Experience on memory subsystem verification and / or performance analysis Strong knowledge of ASIC flow, RTL design in Verilog, System Verilog and FPGA design Knowledge of AXI, DFI protocols Working knowledge of memory controller and memory PHY We’re doing work that matters. Help us solve what others can’t. #J-18808-Ljbffr

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