Sr. ASIC Design Engineer

Positron.ai specializes in developing custom hardware systems to accelerate AI inference. These inference systems offer significant performance and efficiency gains over traditional GPU-based systems, delivering advantages in both performance per dollar and performance per watt. Positron exists to create the world's best AI inference systems. Position : Senior ASIC Design EngineerCompany : Positron.aiJob Type : Full-timeReports To : Director of ASIC EngineeringLocation : Remote Position Overview As a Senior ASIC Design Engineer, you will take a leadership role in defining, implementing, and delivering critical IP blocks and subsystems for Positron.ai’s inference ASICs/SoCs. You will own the microarchitecture from high-level concept through RTL signoff, collaborating across architecture, verification, and physical design to achieve ambitious PPA and schedule goals. In addition to hands-on SystemVerilog design, you will mentor junior engineers, influence methodology, and drive key architectural tradeoffs that impact silicon performance and efficiency. Key Responsibilities Define and document microarchitecture for complex IP blocks/subsystems. Deliver production-quality, parameterized SystemVerilog RTL with well-defined interfaces, power/clock intent, and embedded assertions. Technical Ownership & Signoff: Lead lint, CDC/RDC, DFT integration, and synthesis bring-up; collaborate with PD on floorplan and timing closure. Own PPA metrics for assigned blocks and drive microarchitectural optimizations to meet targets. Advanced Interface & Memory Integration: Architect and integrate high-performance interconnects (AXI/CHI/ACE), DMA engines, coherency logic, and high-speed memory interfaces (HBM/DDR). Engage with IP vendors and internal stakeholders to ensure seamless integration. Develop and enforce coding guidelines, reusable IP packaging, and signoff checklists. Contribute automation flows (Python/Tcl/Make/CI) to improve team efficiency. Cross-Functional Collaboration: Partner closely with Verification to define test plans and reference models. Work with Architecture and Performance teams to correlate models against RTL. Support bring-up, post-silicon debug, and customer engagements as required. Mentorship & Technical Leadership: Guide junior engineers in design techniques, methodology, and problem-solving. Lead design reviews, drive consensus on tradeoffs, and advocate for best-in-class solutions. Required Qualifications BS/MS in EE/CE (or related) with 8+ years of ASIC/SoC RTL design experience on complex, high-performance silicon. Proven track record of leading designs from spec → microarchitecture → RTL → signoff with strong PPA outcomes. Deep SystemVerilog RTL expertise, including clocking, resets, CDC/RDC handling, and protocol correctness. Extensive experience with front-end flows/tools (lint, CDC, synthesis/STA, DFT) using major EDA suites. Hands‑on expertise with at least three of: HBM/DDR, PCIe/CXL, AMBA AXI/ACE/CHI, cache/memory hierarchies, high-throughput datapaths. Strong cross‑functional communication skills, capable of leading technical discussions and producing clear specifications. Preferred Qualifications Background in AI/ML accelerator design (matrix/vector engines, compression, NoC bandwidth planning). Formal verification/SVA expertise for property checking and design assertions. Experience with low‑power design techniques (clock-/power‑gating, UPF/CPF). Collaboration experience with cocotb/UVM for checkers and reference model co‑development. Familiarity with RISC‑V subsystems, coherence protocols, or customer‑owned tooling (COT) flows. Why Join Us? Shape the next generation of AI inference hardware with a high‑caliber, collaborative team. Take technical ownership of critical silicon components that directly impact product success. Competitive salary + equity, comprehensive benefits, and flexible work environment. Opportunities to innovate, lead, and grow your influence in a rapidly evolving space. Interested? Apply with your resume and a brief note describing a block or subsystem you led from concept to tape‑out, highlighting the PPA challenges you addressed and the architectural tradeoffs you drove. #J-18808-Ljbffr