Senior Design Engineer

Lattice Overview
There is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a "team first" organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for.

Responsibilities & Skills
The position is for Integration Design Engineer at Lattice Semiconductor (PH) Corp. The design engineer will be part of the Silicon Integration Team and will mainly be responsible for the integration of different IPs to build the chip utilizing both custom and digital design flows.

Accountabilities

• Design engineer will generally be responsible for the integration of different IPs to build the fullchip. This extends to the delivery of all the corresponding models, views and collaterals to different functional teams and the completion of all the required checks and simulations for sign-off.
• Collaborate with Architecture, SW, IP Design, and Physical Design Teams to generate fullchip logical floorplan. Generate fullchip behavioral model by integrating the various IP models in alignment to the logical floorplan and the requirements of SW and Verification teams. Responsibility extends to the delivery of fullchip synthesized netlist and fullchip schematics.
• Design and implement (custom and digital) density-specific IPs (such as clock networks) and sectors (group of IPs) suitable for fullchip integration. Perform all flows and checks such as elaboration/compilation, synthesis, equivalence, DFT, timing closure (spice simulation and/or STA), power and performance analysis.
• Work closely with other functional teams to debug and resolve issues.
• Perform fullchip tapeout-gating audits such as Electromigration and IR drop (EMIR) Analysis, Netlist Electrical Rule Checks (NetERC), Power Distribution Network (PDN) Extraction, Simultaneously Switching Outputs (SSO) simulations, and ESD checks.

Required Skills- BS or MS in Electronics/Computer/Electrical Engineering
- At least 5 years of proven in-depth experience in Custom and Digital Design Implementation. Expertise in Verilog and System Verilog is a must.
- Experience in FPGA/CPLD design and integration is a plus.
- Expertise/Solid understanding of the following:
- Custom Design Flow
- Semiconductor principles and transistor-level analysis
- Industry standard tools for schematic and layout Entry (Cadence Virtuoso)
- Characterization, performance, and power simulations (spice is preferred)
- Digital Design Flow

• RTL coding and verification
• Lint Check, Elaboration/Compilation, Synthesis, Equivalence Check, SDC, and STA using industry standard tools (Xcelium, Genus, Innovus, Tempus)
• Knowledge in DFT flow and ATPG generation is an advantage.
• Experience in IP and Fullchip functional verification is a plus.
• Expertise in coding/scripting (Perl, TCL, Shell, Skill, Phyton)
• Experience in project leadership and product development cycle (planning, resourcing, tapeout, silicon characterization/validation) is a plus.