Experienced Design Verification

6 days ago

Ayala Alabang, National Capital Region, Philippines SilVerSSC Full time ₱900,000 - ₱1,200,000 per year

Join Silicon Verified Consultancy Inc.

QUALIFICATIONS Experienced Design Verification Engineer

  • 5 to 10 years working experience in Front-End Design Verification with proven ability to actively contribute to IP-level digital logic design, implementation, and verification projects from a chip/sub-system/sub-block level using:

  • SystemVerilog in a UVM environment;

  • ASIC/FPGA/SOC design flow/development cycle;
  • EDA simulation tools like Synopsys VCS, Mentor Questa, or Cadence IES/XCELIUM
  • Robust debugging and problem-solving skills supported by relevant bug reporting/fixing experience.

  • Having the following skills would be an advantage:

  • RTL Design/Digital Implementation

  • Chip-level FW co-verification using C tests in UVM environment
  • Formal Property Verification
  • Automation using Shell Scripting, Make, Python or Perl

  • Familiarity with or Experience in two or more of the following:

  • NVMe, PCIe, or Advanced Microcontroller Bus Architecture (AMBA) standards;

  • Functional Verification and/or RTL design of Memory Controller, Error Detection & Correction, Error Correction Codes (ECC), Security & Cryptography blocks.
  • Excellent written and verbal communication skills.
  • Having an active nonimmigrant US visa or Canada visa/eTA is a plus.

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