Integration Design Engineer

Integration Design Engineer Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists partnering with world‑class sales, marketing, and support teams. We develop programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and we bring total commitment and a keen competitive personality to every project. Energy feeds on energy. If you thrive in a fast‑paced, results‑oriented environment, want to achieve individual success within a “team first” culture, and believe you can contribute and succeed in a demanding yet collegial atmosphere, Lattice may be just what you’re looking for. Accountabilities Design engineer will generally be responsible for the integration of different IPs to build the full‑chip. This extends to the delivery of all the corresponding models, views and collaterals to different functional teams and the completion of all the required checks and simulations for sign‑off. Collaborate with Architecture, SW, IP Design, and Physical Design Teams to generate full‑chip logical floorplan. Generate full‑chip behavioral model by integrating the various IP models in alignment with the logical floorplan and the requirements of SW and Verification teams. Responsibility extends to the delivery of full‑chip synthesized netlist and full‑chip schematics. Design and implement (custom and digital) density‑specific IPs (such as clock networks) and sectors (group of IPs) suitable for full‑chip integration. Perform all flows and checks such as elaboration/compilation, synthesis, equivalence, DFT, timing closure (spice simulation and/or STA), power and performance analysis. Work closely with other functional teams to debug and resolve issues. Perform full‑chip tape‑out‑gating audits such as Electromigration and IR drop (EMIR) Analysis, Netlist Electrical Rule Checks (NetERC), Power Distribution Network (PDN) Extraction, Simultaneously Switching Outputs (SSO) simulations, and ESD checks. Required Skills BS or MS in Electronics/Computer/Electrical Engineering At least 8 years of proven in‑depth experience in Custom and Digital Design Implementation. Expertise in Verilog and System Verilog is a must. Experience in FPGA/CPLD design and integration is a plus. Expertise on the following: Semiconductor principles and transistor‑level analysis Industry standard tools for schematic and layout Entry (Cadence Virtuoso) Characterization, performance, and power simulations (spice is preferred) Digital Design Flow RTL coding and verification Lint Check, Elaboration/Compilation, Synthesis, Equivalence Check, SDC, and STA using industry standard tools (Xcelium, Genus, Innovus, Tempus) DFT flow and ATPG generation Experience in IP and full‑chip functional verification is a plus. Expertise in coding/scripting (Perl, TCL, Shell, Skill, Phyton) Experience in project leadership and product development cycle (planning, resourcing, tape‑out, silicon characterization/validation) is a plus. Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. We continually strive to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry. Lattice is an international, service‑driven developer of innovative low‑cost, low‑power programmable design solutions. Our global workforce, some 800 strong, shares a total commitment to customer success and an unbending will to win. For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit . You can also follow us via Twitter, Facebook, or RSS. Applications are welcome from all qualified candidates. Seniority level: Mid‑Senior level Employment type: Full‑time Job function: Engineering and Information Technology Industries: Semiconductor Manufacturing Location: Muntinlupa City, National Capital Region, Philippines #J-18808-Ljbffr