
Senior Design Engineer
22 hours ago
Overview
We are looking for an experienced Senior Design Engineer to drive the RTL-to-GDSII flow , focusing on timing analysis, floor-planning, place and route, timing closure, power analysis, and power grid optimization for mature and advanced technology nodes. This role involves backend design implementation for ASIC/FPGA , resource planning , team development , and project leadership to ensure successful client deliveries.
Key Responsibilities- Develop and implement low-power physical designs , including logic synthesis, STA, power analysis, IR drop, EM, and verification .
- Identify and resolve power and performance issues , driving methodology improvements.
- Conduct PPA benchmarking and ensure robustness of design flow.
- Lead and manage design projects , ensuring on-time, high-quality deliverables .
- Provide mentorship, coaching, and technical guidance to project teams.
- Implement flow development and automation using Perl, TCL, Python , etc.
- BS in Electrical Engineering, Electronics Engineering, Computer Engineering, or Applied Physics .
- 5+ years of experience in physical design and backend implementation .
- Hands-on experience with multiple tapeouts in mature and advanced nodes.
- Expertise in timing closure, power integrity, signal integrity, and physical verification .
- Proficiency in EDA tools (e.g., Design Compiler, PrimeTime, ICC2, Innovus, Redhawk, Voltus ).
- Strong scripting skills (Shell, Tcl, Perl, Python ).
- Experience in low-power design techniques (power gating, multi-VT, voltage scaling).
- Knowledge of RTL-to-GDSII methodologies , including ECO, EM, IR analysis, and reliability checks
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