Staff Design Verification Engineer

Lattice Overview
There is energy here…energy you can feel crackling at any of our international locations. It's an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a "team first" organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you're looking for.

Responsibilities
Responsibilities & Skills
Inviting candidates with a passion for invention and self-challenge. This position gives you an opportunity to be a part of one of the most cutting edge and key projects that Lattice's Silicon Engineering team has embarked upon to date. As part of our team, you will have the opportunity to contribute to verifying complex FPGAs.

This team will allow you to integrate multiple sophisticated IP level Design and Verification (DV) environments, craft highly reusable best-in-class UVM TB, implement effective coverage driven and directed test cases, deploy new tools and implement methodologies to improve quality of tape-out readiness. By collaborating with other product development teams across Lattice, you can push the industry boundaries of what FPGA systems can do and improve the product experience for our customers across the world

You will be able to learn all aspects of a FPGA, different types of SOC architecture, many highspeed layered protocols, industry's standard methodologies on low power architecture, best in class DV methodology, verification on accelerated platforms, FW-HW interactions, complexities of FPGA and SOC debug architecture, etc. You'll be at the center of the design verification effort within our silicon design SOC verification team responsible for crafting and productizing state-of-the-art FPGAs.

This position requires someone comfortable will all areas of FPGA design verification engineering. Someone that thrives in a dynamic multi-functional organization and is not afraid to take on challenges and solve complex problems using state of the art verification methodologies.

Required Skills

• BS/MS Electrical Engineering, Computer Science, Computer Systems Engineering, or equivalent degree
• At least 8+ years DV experience out of which 3+ years as leading a complex IP verification
• Proven track record of working full ASIC verification from concept to tape-out
• Advanced knowledge of System Verilog and UVM methodology
• Experience in using programming languages such as C/C++, Perl/Python/Tcl for automatic the DV tasks
• Hands-on verification experience in verifying IPs like PCIExpress, Ethernet or USB in UVM environment will be big plus.
• Hands-on verification experience in verifying IPs using AMBA bus architecture in UVM environment.
• Hands-on verification experience in verifying the firmware used for SOC functions
• In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification.
• .Ability to create IP level module and sub-system verification plans, TBs, portable test benches, sequences, verification infrastructure.
• Develop UVM based highly reusable test benches and integrate complex multi-instance VIPs, sub-system test benches and verification suites at SOC level, and achieve targeted coverage
• Work with design, architecture, SW, FW, and IP delivery teams to efficiently integrate and verify overall FPGA design.
• Should be a great team leader with excellent communication and problem-solving skills and the desire to seek diverse challenges.