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Chip Design Specialist
1 week ago
We are a worldwide community of engineers, designers, and manufacturing operations specialists who develop programmable logic solutions that change the industry. Our focus is on R&D, product innovation, and customer service, with total commitment and a keenly sharp competitive personality.
Responsibilities & SkillsThe position is for Integration Design Engineer at Lattice Semiconductor Corp. The design engineer will be part of the Silicon Integration Team and will mainly be responsible for the integration of different IPs to build the chip utilizing both custom and digital design flows.
Key Accountabilities:
- Design engineer will generally be responsible for the integration of different IPs to build the fullchip. This extends to the delivery of all the corresponding models, views and collaterals to different functional teams and the completion of all the required checks and simulations for sign-off.
- Collaborate with Architecture, SW, IP Design, and Physical Design Teams to generate fullchip logical floorplan. Generate fullchip behavioral model by integrating the various IP models in alignment to the logical floorplan and the requirements of SW and Verification teams. Responsibility extends to the delivery of fullchip synthesized netlist and fullchip schematics.
- Design and implement (custom and digital) density-specific IPs (such as clock networks) and sectors (group of IPs) suitable for fullchip integration. Perform all flows and checks such as elaboration/compilation, synthesis, equivalence, DFT, timing closure (spice simulation and/or STA), power and performance analysis.
- Work closely with other functional teams to debug and resolve issues.
- Perform fullchip tapeout-gating audits such as Electromigration and IR drop (EMIR) Analysis, Netlist Electrical Rule Checks (NetERC), Power Distribution Network (PDN) Extraction, Simultaneously Switching Outputs (SSO) simulations, and ESD checks.
Required Skills:
- Bachelor's or Master's degree in Electronics, Computer, or Electrical Engineering.
- At least 5 years of experience in Custom and Digital Design Implementation. Expertise in Verilog and System Verilog is essential.
- Experience in FPGA/CPLD design and integration is desirable.
- Expertise in semiconductor principles, transistor-level analysis, and characterization, performance, and power simulations.
- Digital Design Flow skills, including RTL coding and verification, lint check, elaboration/compilation, synthesis, equivalence check, SDC, and STA using industry standard tools.
- Knowledge in DFT flow and ATPG generation is an advantage.
