
Expert in Mixed Signal IC Design Verification
2 days ago
We are seeking a seasoned verification engineer to join our team.
The ideal candidate will have extensive experience in design verification, with a strong background in leading edge verification methodologies. They will be responsible for verifying complex designs and sub-systems, as well as contributing to the development of verification plans and testbenches.
Key responsibilities include:
- Verification of complex designs and sub-systems using advanced verification techniques
- Development of verification-plans, functional coverage, tests and verification methodology for block/chip-level verification
- Debugging of Gate Level Simulation (GLS), waiving Timing Violations approved by designer
- Continuous interaction with analog co-sim and firmware team
- Mentorship and guidance of junior verification engineers on SoC Verification
Requirements:
- Bachelor's or master's degree in Electronic Engineering or equivalent
- 5-10 years of experience in ASIC design verification
- Strong knowledge of verification-plan generation, coverage analysis, constrained random techniques, assertion-based and formal verification techniques with System Verilog
- Proficiency in developing unit and SoC level test benches using UVM
Preferred qualifications include:
- Experience with HW emulation or FPGA prototyping
- Experience in behavioural modelling of analogue circuits
- Experience in verifying processor based designs
- Knowledge of interface protocols e.g. AHB/APB/AXI/I2C/SPMI
This is an excellent opportunity to work on challenging projects and develop your skills in design verification.
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