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Staff IC Design and Verification Engineer
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The Staff IC Layout Designer will work with IC Design Engineers in 3 design sites, including the USA, the UK, and Switzerland, to implement circuit schematics in physical layout. This role will work with Technology Engineers to implement circuit components such as transistors, resistors, capacitors, etc., as well as test structures in physical layout. In addition, this individual will verify completed physical layout using CAD tools such as Cadence Layout and Schematic editor, and Mentor Calibre DRC and LVS. Carry out all necessary tasks in preparing and taping out the verified layout database to mask shop.
Requirements- BSEE preferred
- IC layout certification required
- A minimum of 8 years of IC layout experience, preferably in analog or mixed-mode IC layout design
