IC Layout Engineer

There is energy here… energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality. Energy feeds on energy. If you flourish in a fast-paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. Creates high-quality analog, mixed-signal, and custom digital layout. Requires at least 2+ years of proven in-depth experience in custom and semi-custom layout of various IPs, including memory and array cells, analog and mixed-signal blocks, Serdes, and chip-level layout integration.

The role includes IP block ownership, sector and full chip task support, chip-level layout integration support, methodology improvement participation, and schedule definition to implement assigned layout tasks. Duties include but are not limited to custom layout of ECO (Engineering Change Order) and LCO (Layout Change Order), physical verification of cells up to chip-level (e.g., DRC, LVS, ESD, DFM, Antenna, EMIR, PERC), meeting or beating task schedules, prompt resolution of layout-related technical issues, clear communication with stakeholders, and administrative tasks such as task schedule definition. Run and analyze parasitic extractions.

• Execute floor plan, routing, and physical verification of custom IPs (analog, mixed-signal, and digital). Create IP layout documentation and support until sign-off.
• Support sector and full chip activities such as physical integration and verification.
• Work effectively with circuit designers to understand key layout constraints.
• Collaborate proactively with EDA CAD group when issues arise.
• Hold layout quality reviews of completed cells, macros, and chip-level layout.
• Recognize layout considerations related to device matching, noise, shielding, and latch-up in analog, mixed-signal, and digital circuits.
• Run and analyze parasitic extractions.

• At least 2 years of solid industry experience in Custom Layout Engineering.
• Experience in custom layout of IP blocks to full chip layout integration using Cadence Virtuoso and full physical verification (DRC, LVS, ESD, Antenna, DFM, EM-IR, PERC) using Siemens Calibre.
• Experience in running, analyzing, and debugging EM-IR using Cadence Voltus.
• Experience in generating LPE is preferred.
• Automation skills such as Cadence SKILL scripting are a plus.
• FinFET technology node experience is a plus.
• PNR experience is a plus.

Lattice recognizes that employees are its greatest asset and the driving force behind success in a highly competitive, global industry. We continually strive to provide comprehensive compensation and benefits to attract, retain, motivate, reward, and celebrate top talent.

Lattice is an international developer of innovative low-cost, low-power programmable design solutions. Our global workforce of approximately 800 employees shares a total commitment to customer success and a strong will to win. For more information on our FPGA, CPLD, and power management devices, visit Follow us on Twitter, Facebook, or RSS. At Lattice, we value diversity and the unique perspectives individuals bring to the workplace. Applications are welcome from all qualified candidates.

Feel the energy.